1. Field of the Invention
The present invention relates to voltage clamping circuits for limiting the voltage range of a signal which would otherwise exceed predetermined maximum and minimum signal peaks, and in particular, to voltage clamping circuits that provide asymmetrical, or unipolar, voltage clamping.
2. Description of the Related Art
As integrated circuits become increasingly complex and the number of functions they perform become more numerous, it becomes increasingly important that such integrated circuits be capable of interfacing with signal sources that generate large or otherwise unusual signals. This is particularly true in mixed signal applications where the integrated circuit is often a digital circuit that operates with binary logic and is powered by a low voltage power supply and yet must be capable of dealing with analog signals which can exceed the voltage or current handling capabilities of the integrated circuit.
For example, integrated circuits for controlling video monitors that use cathode ray tubes (CRTs), such as those typically used with personal computers, must be able to work with many types of large signals. One example would be the horizontal and vertical flyback pulses generated during the horizontal and vertical retrace intervals, respectively, of the video display. Referring to FIG. 1, in the case of the horizontal flyback pulses, such pulses can be in the range of 100 volts peak-to-peak, with much of the signal being positive but also some of the signal being negative with respect to the system reference, or ground.
Referring to FIG. 2, the integrated circuit that must deal with such high magnitude signal pulses will have an internal amplifier stage A1 which is responsible for converting such pulses into a digital pulse stream. An external resister Rext will be used to limit the input current to the integrated circuit to a predetermined maximum positive value during the flyback interval and a predetermined negative value during the normal forward scan interval. Typically, diodes D1, D2 are also used at the input terminal to provide protection against electrostatic discharge (ESD) events in accordance with well-known techniques. The digital pulses HBLANK are for use elsewhere in the system for things such as blanking the video signal within the video amplifier and synchronizing a phase lock loop used in an on-screen display (OSD) generator.
Referring to FIG. 3, it is desirable that the digital output pulse HBLANK should trigger to its high signal state before the rising edge of the flyback pulse has passed through the zero volt level (time interval t1). Similarly, it is desirable that it then trigger to its low signal state soon after falling below the zero volt level (time interval t2).
Since the integrated circuits used in such an application are typically powered by a signal-ended power supply, such as a positive five volt power supply, it is important that the negative signal excursions of the input flyback signal HFLYBACK somehow be prevented from affecting the input terminal of the integrated circuit. As is well know, such negative signal excursions can cause current to flow within the substrate of the integrated circuit due to a reverse current flow at the input terminal. Accordingly, it would be desirable to have some form of voltage clamping circuit which provides asymmetrical, or unipolar, clamping of the input signal to prevent a negative voltage from appearing at the input terminal notwithstanding any negative voltage excursions of the input signal. (The term unipolar as used herein in intended to mean those signals having peak values within the range of zero to a positive voltage, inclusive, or zero to a negative voltage, inclusive.)